1. Field of the Invention
The present disclosure generally relates to the field of fabricating integrated circuits, and, more particularly, to interconnect structures for connecting different device levels by vias extending through the substrate material of the devices.
2. Description of the Related Art
In modern integrated circuits, a very high number of individual circuit elements, such as field effect transistors in the form of CMOS, NMOS, PMOS elements, resistors, capacitors and the like, are formed on a single chip area. Typically, feature sizes of these circuit elements are reduced with the introduction of every new circuit generation, to provide currently available integrated circuits formed by volume production techniques with critical dimensions of 50 nm or less and having an improved degree of performance in terms of speed and/or power consumption. A reduction in size of transistors is an important aspect in steadily improving device performance of complex integrated circuits, such as CPUs. The reduction in size is commonly associated with an increased switching speed, thereby enhancing signal processing performance at transistor level.
In addition to the large number of transistor elements, a plurality of passive circuit elements, such as capacitors, resistors, interconnect structures and the like, are typically formed in integrated circuits as required by the basic circuit layout. Due to the decreased dimensions of the active circuit elements, not only the performance of the individual transistor elements may be improved, but also their packing density may be increased, thereby providing the potential for incorporating more and more functions into a given chip area. For this reason, highly complex circuits have been developed, which may include different types of circuits, such as analog circuits, digital circuits and the like, thereby providing entire systems on a single chip (SoC).
Although transistor elements are the dominant circuit elements in highly complex integrated circuits which substantially determine the overall performance of these devices, other components such as capacitors and resistors, and in particular a complex interconnect system or metallization system, may be required, wherein the size of these passive circuit elements may also have to be adjusted with respect to the scaling of the transistor elements in order to not unduly consume valuable chip area.
Typically, as the number of circuit elements, such as transistors and the like, per unit area increases in the device level of a corresponding semiconductor device, the number of electrical connections associated with the circuit elements in the device level is also increased, typically even in an over-proportional manner, thereby requiring complex interconnect structures which may be provided in the form of metallization systems including a plurality of stacked metallization layers. In these metallization layers, metal lines, providing the inner level electrical connection, and vias, providing intra level connections, may be formed on the basis of highly conductive metals, such as copper and the like, in combination with appropriate dielectric materials so as to reduce the parasitic RC (resistive capacitive) time constants, since, in sophisticated semiconductor devices, typically, signal propagation delay may be substantially restricted by the metallization system rather than the transistor elements in the device level. However, expanding the metallization system in the height dimension so as to provide the desired density of interconnect structures may be restricted by the parasitic RC time constants and the limitations imposed by the material characteristics of sophisticated low-k dielectrics. That is, typically, a reduced dielectric constant is associated with reduced mechanical stability of these dielectric materials, thereby also restricting the number of metallization layers that may be stacked on top of each other in view of yield losses during the various fabrication steps and the reduced reliability during operation of the semiconductor device. Thus, the complexity of semiconductor devices provided in a single semiconductor chip may be restricted by the capabilities of the corresponding metallization system and in particular by the characteristics of sophisticated low-k dielectric materials, since the number of metallization layers may not be arbitrarily increased.
For this reason, it has also been proposed to further enhance the overall density of circuit elements for a given size or area of a respective package by stacking two or more individual semiconductor chips, which may be fabricated in an independent manner, however, with a correlated design so as to provide, in total, a complex system while avoiding many of the problems encountered during the fabrication process for extremely complex semiconductor devices on a single chip. For example, appropriately selected functional units, such as memory areas and the like, may be formed on a single chip in accordance with well-established manufacturing techniques including the fabrication of a corresponding metallization system, while other functional units such as a fast and powerful logic circuitry may be formed independently as a separate chip, wherein, however, respective interconnect systems may enable a subsequent stacking and attaching of the individual chips so as to form an overall functional circuit, which may then be packaged as a single unit. Thus, a corresponding three-dimensional configuration may provide increased density of circuit elements and metallization features with respect to a given area of a package, since a significant larger amount of the available volume in a package may be used by stacking individual semiconductor chips. Although this technique represents a promising approach for enhancing volume packing density and functionality for a given package size for a given technology standard while avoiding extremely critical manufacturing techniques, for instance in view of stacking a large number of highly critical metallization layers, appropriate contact elements have to be provided to enable the electrical connections of the individual semiconductor chips in a reliable and well-performing manner. To this end, it has been suggested to form through hole vias through the substrate material of at least one of the chips so as to enable electrical contact to respective contact elements of a second semiconductor chip, while the metallization system of the first semiconductor chip may further be available for connecting to other semiconductor chips or a package substrate and the like. These through hole vias, which are also referred to as through silicon vias (TSV), may typically represent contact elements of a high aspect ratio, since the lateral dimensions of these vias may also be reduced in view of saving valuable chip area, while on the other hand the thickness of the substrate material may not be arbitrarily reduced. Additionally, in view of electrical performance, the conductivity of the through hole vias should be maintained at a high level so as to accommodate the required high current densities and also reduce signal propagation delay in systems in which exchange of electrical signals between individual semiconductor chips may have to be accomplished on the basis of moderately high clock frequencies.
In view of this situation, in conventional approaches, the corresponding high aspect through hole vias may be formed on the basis of well-established manufacturing techniques also known from the fabrication of contact structures and metallization systems, which may involve the etching of respective openings, such as via openings and trenches in a moderately thin dielectric material and the subsequent filling of these openings with metal-containing materials, such as copper in combination with conductive barrier materials, such as titanium nitride, tantalum nitride, tantalum and the like. By transferring a corresponding technology to a fabrication sequence for through hole vias, appropriate high conductivity values may be obtained in conformity with requirements with respect to enhanced electrical performance.
Consequently, a plurality of process strategies have been developed in which deep openings are formed in the silicon substrate at any appropriate manufacturing stage and wherein these openings are then filled with materials as are typically used for forming the metallization system of the semiconductor device under consideration. For example, via holes may be formed in the front side of the silicon substrate or the via holes may be formed in any appropriate metallization layer so as to extend deeply into the silicon substrate, wherein the via holes may be opened from the rear side of the substrate prior to or after filling in appropriate metal-containing materials, such as conductive barrier layers in combination with copper and the like. In other cases, the through hole vias may be formed from the rear side of the substrate at any appropriate manufacturing stage that is compatible with the overall manufacturing flow for forming circuit elements and the like. Consequently, the through hole vias may provide superior connectivity between critical circuit portions, which may be efficiently formed on different device levels or different semiconductor chips, which may be efficiently stacked on top of each other, wherein the substantially vertical connection may provide reduced parasitic capacitance and resistance. Furthermore, increased volume packing density may be accomplished for a given lateral area of a package so that very complex electronic systems may be integrated into a single package, while at the same time complexity of individual circuit portions or device portions, such as metallization systems and the like, may be reduced.
Although the three-dimensional stacking of device levels or semiconductor chips is a very promising approach for enhancing performance of complex integrated circuits, however, the thermal mismatch in the coefficient of thermal expansion between the through hole vias and the silicon substrate may result in severe damage and thus failures of complex semiconductor devices, as will be described in more detail with reference to FIG. 1.
FIG. 1 schematically illustrates a cross-sectional view of a semiconductor device 100, which may represent a part of a complex integrated circuit to be provided as a three-dimensional stacked configuration. The semiconductor device 100 comprises a substrate 101, such as a silicon substrate, since presently complex semiconductor devices are being made and will be made in the near future on the basis of a silicon material. The silicon substrate 101 has a rear side 101R, which is to be contacted with a further semiconductor device, a carrier substrate and the like, in order to provide a stacked device configuration. Furthermore, the substrate 101 comprises a front side 101F above which is typically provided a semiconductor layer, such as a silicon layer 102, in and above which are typically provided circuit elements 103, such as transistors and the like. It should be appreciated, however, that circuit elements, such as capacitors and the like, may also be frequently provided within the substrate 101, that is, at or near the front side 101F. For convenience, any such circuit elements formed within the substrate 101 are not shown in FIG. 1. It should further be noted that the circuit elements 103 may be formed on the basis of critical dimensions of 50 nm and even less, when sophisticated devices such as CPUs, advanced memory devices and the like are considered. Furthermore, the semiconductor device 100 may comprise a metallization system 110, which is to be understood as one or more metallization layers in which metal lines are provided to establish the electrical connections between the individual circuit elements 103 in accordance with the circuit layout under consideration. Typically, as discussed above, a plurality of metallization layers 111, 112 and 113 are necessary to establish the required electrical connection. For convenience, any specific configuration of these metallization layers is not shown in FIG. 1 and significantly depends on the overall device requirements. For example, in sophisticated applications, highly conductive metals such as copper and the like are used as metal, in combination with conductive barrier material systems such as tantalum, tantalum nitride, titanium, titanium nitride and the like. Furthermore, complex dielectric materials such as ULK materials and low-k dielectric materials are frequently used to enhance the overall performance of the metallization system 110. Furthermore, the semiconductor device 100 comprises through hole vias 120A, 120B, which may also be referred to as through silicon vias (TSV), which, in the manufacturing stage shown, may extend through at least a portion of the metallization system 110, through the semiconductor layer 102 and deeply into the substrate 101. For example, in the process strategy as illustrated in FIG. 1, the through hole vias 120A, 120B may connect to the rear side 101R by removing a portion of the substrate 101 so as to finally expose a portion of the through hole vias 120A, 120B, as is indicated by the dashed line in FIG. 1. As discussed above, however, any other process strategy may be applied wherein the through hole vias 120A, 120B may have basically the same configuration. In the example shown, the vias 120A, 120B may comprise an insulating material layer 121, such as a silicon dioxide material and the like, which may separate a conductive fill material from the material of the substrate 101 in order to reliably electrically isolate the vias 120A, 120B. In the example shown, a conductive barrier material 122, such as a material system comprised of tantalum and tantalum nitride, may be provided in combination with a highly conductive core metal 123, such as copper, when these materials are also used in the metallization system 110.
The semiconductor device 100 as illustrated in FIG. 1 may be formed on the basis of any appropriate process strategy. For example, the circuit elements 103 may be formed in and above the silicon layer 102 in accordance with well-established process strategies in order to obtain the circuit elements based on the design rules for the device 100. Thereafter, the metallization system 110 may be formed by forming the metallization layers 111, 112 based on the deposition of sophisticated dielectric materials and patterning the same so as to form corresponding lines and via openings therein, which are subsequently filled with appropriate conductive materials, such as tantalum, tantalum nitride, copper and the like. At any appropriate stage, also openings for the through hole vias 120A, 120B may be formed through the metallization system 110 and these openings may be formed so as to extend through the layer 102 and into the substrate 101, as illustrated in FIG. 1. It should be appreciated that, during a corresponding complex etch process, other device areas may be efficiently masked by polymer materials such as resist materials and the like. Furthermore, a plurality of well-established etch recipes are available in order to form openings into the substrate 101 having any appropriate shape and lateral size, depending on the requirements for the through hole vias 120A, 120B. For example, the corresponding holes may be formed with a lateral size of 15-20 μm or greater, wherein the lateral size may vary with the depth of the corresponding via holes. As discussed above, the via holes may be formed so as to extend to a certain depth, wherein the bottom of the through hole vias 120A, 120B may be exposed by removing material from the rear side 101R at any later manufacturing stage, wherein also an appropriate metallization system may be provided at the rear side 101R after the material removal in order to appropriately connect to the through hole vias 120A, 120B and to provide an appropriate bump structure so as to contact a further contact structure of a semiconductor device, a carrier substrate and the like. After forming the deep via holes, insulating material 121 is typically provided, for instance by appropriate deposition processes, followed by the deposition of the conductive barrier material 122 and the highly conductive core metal 123, which may be accomplished by applying well-established deposition techniques, such as chemical vapor deposition (CVD) for the layer 121, CVD or sputter deposition for the layer or layer system 122 and electrochemical deposition techniques for the core material 123. It should be appreciated that, if required, an additional seed layer, such as a copper layer, may be provided after the deposition of the conductive barrier material 122, which may also be accomplished on the basis of sputter deposition, electrochemical deposition and the like. In particular during the deposition of the core metal 123, an efficient bottom-to-top fill behavior is accomplished on the basis of pulse reverse regimes used during an electroplating process, thereby substantially void-free filling in the core metal 123. Thereafter, any excess material may be efficiently removed, for instance by chemical mechanical polishing (CMP), electro etching and the like. Thereafter, any further metallization layers, such as the layer 113, may be provided so as to appropriately contact the through hole vias 120A, 120B and also other components of the metallization system 110.
During the further processing and also during operation of the semiconductor device 100, once it may be incorporated in a three-dimensional stacked device configuration, the mismatch of the coefficients of thermal expansion of the through hole vias 120A, 120B and the substrate 101 may result in device failures, for instance caused in the metallization system 110 and/or in the device level 102, that is, in the vicinity of the front side 101F of the substrate 101. As is well known, the coefficient of thermal expansion of metals, such as copper, is several times greater than the thermal expansion coefficient of, for instance, silicon material, which may thus result in severe thermally induced stress caused by the different change in volume of the through hole vias 120A, 120B with respect to the substrate material 101. For example, as indicated by 123V, a significant increase in volume may occur upon elevated temperatures which may be induced during the further processing of the device 100 and/or during operation of the device 100, thereby resulting in significant mechanical stress, since the core metal 123 may be efficiently coupled to the surrounding materials by means of the barrier material system 122. For example, upon expanding in a vertical direction, severe damage may occur in the metallization system 110, as indicated by 110S, thereby even initiating a certain degree of lift-off of one or more of the metallization layers, such as the metallization layer 113. In other cases, in addition to the damage 110S, significant stress components may be exerted to the substrate 101 and also to the device level 102, which may cause cracks and material delamination events, indicated as 102S, which may also contribute to significant device failures in the circuit elements 103, which may comprise highly sophisticated components formed on the basis of critical dimensions of 50 nm and significantly less. It should be appreciated that similar stress conditions may also be induced in cold temperature environments, wherein the shrinkage of the conductive core metal 123 may be significantly greater compared to the substrate material 101, thereby significantly restricting the applicability of the semiconductor device 100 in terms of sophisticated environmental conditions.
The present disclosure is directed to various methods and devices that may avoid, or at least reduce, the effects of one or more of the problems identified above.